1. Field of the Invention
The present invention relates to a semi-flash type A/D (Analog to Digital) converter and semi-flash type A/D converting method, and, more particularly, a semi-flash type A/D converter and semi-flash type A/D converting method which is insusceptible to noise.
2. Description of the Related Art
A semi-flash type A/D converter has a plurality of comparators, and successively performs comparison by a plurality of bits using the comparators to convert an analog signal into a digital signal. As this A/D converter successively performs comparison by a plurality of bits, it can convert an analog signal into a digital signal faster than an ordinary successive comparison type A/D converter.
An example of the structure of a conventional semi-flash type A/D converter will be described referring to FIG. 1. FIG. 1 shows the structure of a semi-flash type 6-bit A/D converter which performs two consecutive comparing operations by three bits. The A/D converter shown in FIG. 1 comprises a D/A converter 101, a selector 102, seven comparators 103 to 109, a sample and hold circuit 110, latches 111 and 112, encoders 113 and 501, and registers 115 and 116 for storage of the conversion results. Signals S0, S1, S2, CLK and EOC are timing signals for controlling the converting operation, and are generated inside this semi-flash type A/D converter.
The D/A converter 101 comprises a plurality of resistors as shown in, for example, FIG. 2. The D/A converter 101 receives signals 200 to 207 from the encoder 113 and outputs signals 210 to 216 and signals 220 to 226. The signals 210 to 216 and signals 220 to 226 have potentials obtained by dividing a difference between a conversion reference potential VREF and a conversion reference ground potential AVSS by resistors. The potentials of the signals 210-216 have the following relationship.
______________________________________ signal 210 &gt; signal 211 &gt; signal 212 &gt; signal 213 &gt; signal 214 &gt; signal 215 &gt; signal 216 ______________________________________
The signals 220-226 are obtained through switches A to H, respectively. The switches A to H are selected in association with the output signals 200-207 from the encoder 113. The potentials of the signals 220-226 have the following relationship.
______________________________________ signal 220 &gt; signal 221 &gt; signal 222 &gt; signal 223 &gt; signal 224 &gt; signal 225 &gt; signal 226 ______________________________________
Table 1 shows the relation between the potentials of the output signals 200-207 of the encoder 113 and those of the signals 220-226, obtained by the actions of the switches A-H.
TABLE 1 __________________________________________________________________________ Function of D/A converter 101 Action of Signal Switches Potentials of Signals 220-226 200 201 202 203 204 205 206 207 A-H Smaller than Larger than __________________________________________________________________________ 1 0 0 0 0 0 0 0 only A ON VREF potential 210 0 1 0 0 0 0 0 0 only B ON potential 210 potential 211 0 0 1 0 0 0 0 0 only C ON potential 211 potential 212 0 0 0 1 0 0 0 0 only D ON potential 212 potential 213 0 0 0 0 1 0 0 0 only E ON potential 213 potential 214 0 0 0 0 0 1 0 0 only F ON potential 214 potential 215 0 0 0 0 0 0 1 0 only G ON potential 215 potential 216 0 0 0 0 0 0 0 1 only H ON potential 216 AVSS __________________________________________________________________________ L level = 0 H level = 1
The selector 102 (FIG. 1) selects the signals 210-216 supplied from the D/A converter 101 while the timing signal S2 is at an L (low) level. While the timing signal S2 is at an H (high) level, the selector 102 selects the signals 220-226 from the D/A converter 101 and supplies the selected signals to inverting input terminals of the comparators 103-109.
An analog signal, which is to be converted into a digital signal, is supplied to an analog input terminal AIN. The sample and hold circuit 110 samples the potential of the analog signal supplied to the analog input terminal AIN during the H-level duration of the timing signal S0, and holds the sampled potential and supplies that potential to the non-inverting input terminals of the comparators 103-109 during the L-level duration of the timing signal S0.
The comparators 103-109 each compare the potentials of the two input signals with each other. Each of the comparators 103-109 outputs an L-level signal when the potential of the signal supplied to the inverting input terminal is higher than that of the signal supplied to the non-inverting input terminal and outputs an H-level signal when the potential of the signal supplied to the inverting input terminal is lower than that of the signal supplied to the non-inverting input terminal.
The latch 111 latches the output signals of the comparators 103-109 while the timing signals S1 and CLK are both at an H level, and holds the latched signals during the other period. The latch 112 latches the output signals of the comparators 103-109 while the timing signals S2 and CLK are both at an H level, and holds the latched signals during the other period.
The encoder 113, which is a logic circuit having a structure as shown in, for example, FIG. 3, produces signals 250 to 252 as well as the signals 200 to 207 from output signals 230 to 236 of the latch 111.
The encoder 501, which is a logic circuit having a structure as shown in FIG. 4, produces signals 253 to 255 from output signals 240 to 246 of the latch 112.
The registers 115 and 116 respectively receive the signals 250-252 and the signals 253-255 during the H-level duration of the control signal EOC, and holds the received signals during the other period.
The function of the flash type A/D converter with the above-described structure will be described with reference to FIGS. 5A through 5K.
The converting operation of the A/D converter in FIG. 1 is executed in three stages of period 1, period 2 and period 3 shown in FIG. 5A.
The operation for each period will be described below.
Operation (S0=H, S1=L and S2=L) in Period 1
The period 1 is a sampling period where an analog input signal is sampled. During this period, the timing signal S0 keeps an H level and the timing signals CLK, S1, S2 and EOC keeps an L level as shown in FIGS. 5A-SE.
As the timing signal S2 has an L level, the selector 102 selects the signals 210-216 from among the output signals of the D/A converter 101 and supplies the selected signals to the comparators 103-109. As the timing signal S0 has an H level, the sample and hold circuit 110 samples the voltage of the analog signal supplied to the analog input terminal AIN.
During this period, the output signals of the comparators 103-109, the signals 230-236, the signals 240-246, the signals 250-256 and the outputs of the registers 115 and 116 respectively keep the same potentials as those of the signals in the previous conversion cycle.
Operation (S0=L, S1=H and S2=L) in Period 2
During the period 2, upper three bits of the 6-bit data corresponding to the analog input signal are obtained.
The timing signal S0 becomes an L level as shown in 5B, so that the sample and hold circuit 110 supplies the potential of the analog input signal sampled in the period 1 to the non-inverting input terminals of the comparators 103-109. As the timing signal S2 keeps the L level as shown in FIG. 5D, the selector 102 selects the signals 210-216 as in the period 1.
The comparators 103-109 respectively compare the potentials of the signals supplied from the selector 102 with the potentials of the signal supplied from the sample and hold circuit 110, and outputs the comparison results as shown in FIG. 5F.
When the outputs of the comparators 103-109 become stable, the timing signal CLK becomes an H level as shown in FIG. 5A. As the timing signal S1 is at an H level as shown in FIG. 5C, the latch 111 latches the output signals of the comparators 103-109 and outputs the signals 230-236 as shown in FIG. 5G.
Upon reception of the signals 230-236, the encoder 113 encodes those signals and outputs the signals 200-207 and the signals 250-252 (see FIG. 5H). The signals 250-252 are upper three bits of the conversion result, the signal 250 indicating the most significant bit (MSB).
As mentioned earlier, the potentials of the signals 210-216 have the relationship of signal 210&gt;signal 211&gt;signal 212&gt;signal 213&gt;signal 214&gt;signal 215&gt;signal 216. In the period 2, therefore, the outputs of the comparators 103-109, the signals 200-207, and the signals 250-252 have signal levels as given in Table 2.
TABLE 2 __________________________________________________________________________ Function of Encoder 113 Outputs of Comparators Signals Signals 103 104 105 106 107 108 109 200 201 202 203 204 205 206 207 250 251 252 __________________________________________________________________________ 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 __________________________________________________________________________ L level = 0 H level = 1
Operation (S0=H, S1=L and S2=H) in Period 3
During the period 3, lower three bits of the 6-bit data corresponding to the analog input signal are obtained.
In the period 3, the timing signal S2 becomes an H level as shown in FIG. 5D, and the selector 102 selects the signals 220-226. At this time, the signals have the signal levels as given in Table 1.
The comparators 103-109 respectively compare signal levels of the signals 220-226 with the signal level of the output of the sample and hold circuit 110, and outputs the comparison results as shown in FIG. 5F.
When the outputs of the comparators 103-109 become stable, the timing signal CLK becomes an H level as shown in FIG. 5A. As the timing signal S2 is at an H level, the latch 111 latches the comparison results and outputs the signals 240-246 as shown in FIG. 5I.
The encoder 501 encodes the signals 240-246, and produces the signals 253-255 as shown in FIG. 5J. The signals 253-255 are lower three bits of the conversion result, the signal 255 indicating the least significant bit (LSB).
When the operation up to this point is complete, the timing signal EOC becomes an H level as shown in FIG. 5E, and at this timing, the register 115 latches the upper three bits of the conversion result while the register 116 latches the lower three bits of the conversion result as shown in FIG. 5K. Through the above operation, one converting operation is completed.
As mentioned earlier, the potentials of the signals 220-226 have the relationship of signal 220&gt;signal 221&gt;signal 222&gt;signal 223&gt;signal 224&gt;signal 225&gt;signal 226. Table 3 shows possible combinations of the outputs of the comparators 103-109, and the relationship between the signals 253-255 association with the combinations.
TABLE 3 ______________________________________ Function of Encoder 501 Outputs of Comparators Signals 103 104 105 106 107 108 109 253 254 255 ______________________________________ 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 1 0 0 0 1 1 1 1 1 0 0 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ______________________________________ L level = 0 H level = 1
TABLE 4 ______________________________________ Function of Encoder 501 Outputs of Comparators Signals 103 104 105 106 107 108 109 253 254 255 ______________________________________ 0 0 0 1 0 1 1 1 1 0 0 1 0 1 1 0 1 1 1 1 0 0 0 1 1 0 1 1 0 1 ______________________________________ L level = 0 H level = 1
The shortcoming of the A/D converter shown in FIG. 1 will now be discussed.
When the difference between the potentials of the two input signals to each of the comparators 103-109 is sufficient large with respect to noise in the A/D converter, the comparators 103-109 can stably perform comparison without being affected by the noise. When the level of the internal noise of the A/D converter is equal to or greater than the difference between the potentials of the two input signals to each of the comparators 103-109, the comparators 103-109 may output erroneous comparison results due to the noise.
Table 4 shows three examples of the relationship between the output signals of the comparators 103-109 and the output signals 253-255 of the encoder 501 when the comparators 103-109 output erroneous signals due to noise. It is apparent from Table 4 that when the output signals of the comparators 103-109 are in error due to noise, the conversion results (253-255) have the wrong values.
To overcome this shortcoming, it is necessary to reduce noise in the A/D converter. With the use of a converter with high resolution precision, it is difficult to sufficiently reduce noise with respect to the resolution level.
Because of the above problem, a semi-flash type A/D converter, which can theoretically perform high-speed conversion at high precision, is actually susceptible to noise and has a difficulty in accomplishing high-precision conversion.